With an increase in Internet connection by recent digital equipment, various functions are implemented on a device by software. Thus, the state of the digital equipment varies according to mainly user's operation. Such states include, for example, the state where extremely high performance and various functions are necessary, the state where high performance is unnecessary but various functions are necessary, and the state where only simple functions with low performance are satisfactory but continuous drive is necessary for a long time.
For instance, while waiting for an email or a phone call, a user is not performing an operation on equipment. In this case, the equipment needs to be operated for a long time, but low performance is acceptable. Thus, a processor which can be operated at a high speed and execute complicated processing or instruction is unnecessary.
Meanwhile, if the user performs an operation such as listening to music, recording music, viewing a video, or recording a video, user's operation on the equipment is not much involved. However, a certain load is continuously applied to the equipment. In this case, there is no need to operate the equipment at a very high speed, but a processor is necessary which can process moderately complicated processing or instruction and maintain a certain processing speed.
Moreover, in browsing the web, writing an email, managing a schedule, creating a memo, or performing other operations, the user actively performs the operation. In this case, operations on the equipment mainly involve, for example, character input, click, and flick. Although load placed on the equipment is not so large, a high response speed is necessary. Thus, complicated processing or instruction is not so much necessary. Meanwhile, a processor which can operate at a high speed, depending on a situation is necessary.
Moreover, when the user, for example, plays games, uses application software handling an image, or uses rich content on the Web, the equipment, for example, changes an image or a sound quickly in response to user's active operation on the equipment. This means that a load on the equipment and a change in load are large on average. In this case, a processor is necessary which can execute complicated processing or instruction and operate at a high speed, depending on a situation.
A current processor for a mobile device (ARM) is a power-saving device, but the performance is not satisfactory. This is because the processor simplifies an executable instruction set for power saving, and the whole processor including an instruction processing unit and an instruction decoder is kept simple.
Moreover, a processor (e.g., Intel and AMD) for a personal computer (PC) is a high-performance processor, but consumes a large amount of power. Such processor has an instruction set including various and complicated instructions, and can execute these instructions. However, this makes, in particular, an instruction processing unit and an instruction decoder complicated and huge.
To improve the above situation, a higher-performance processor has been newly developed for a mobile device (ARM), and this processor and a processor which can be operated with low power consumption are both installed to switch between these processors, depending on a situation (e.g., big.LITTLE and Tegra3). FIG. 12 illustrates an example of a processor including high-performance processors (e.g., CPUs 0 to 3) and a processor which can be operated with low power consumption (e.g., CPU 5).
Moreover, the configuration of a processor for a PC (e.g., Intel and AMD) is simplified to some extent (Atom and Bobcat) so that a reduction in amount of power consumption is more significant than a decrease in performance.
Moreover, as FIG. 13 illustrates, a processor has been suggested which concurrently uses an instruction decoder which can decode an instruction executed for a short time, at a high speed and an instruction decoder which can decode an instruction executed for a long time, at a low speed with low power consumption (e.g., Patent Literature 1).
Moreover, as FIG. 14 illustrates, a processor has been suggested which includes at least one fixed circuit decoder which can decode only part of instructions and at least one execution circuit which executes an instruction, and decodes an instruction which cannot be decoded by the fixed circuit decoder, using a decoder which uses one microcode ROM, to execute the decoded instruction in the execution circuit (e.g., Patent Literature 2).